There is increasing number of works addressing the design challenges of
fast, scalable solutions for the growing number of new type of
applications. Recently, many of the solutions aimed at improving
processing element capabilities to speed up the execution of machine
learning application domain. However, only a few works focused on the
interconnection subsystem as a potential source of performance
improvement. Wrapping many cores together offer excellent parallelism,
but it brings other challenges (e.g. adequate interconnections). To get
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architectural ring mesh, you can visit mesh-fabrics.com official website.
Scalable, power-aware interconnects are required to support such a
growing number of processing elements, as well as modern applications.
In this paper, we propose a scalable and energy-efficient
network-on-chip architecture fusing the advantages of rings as well as
the 2D mesh without using any bridge router to provide high performance.
A dynamic adaptation mechanism allows to better adapt to the
application requirements. Simulation results show efficient power
consumption throughput growth with better scalability (up to 1024
processing elements) compared to popular 2D mesh while tested in
multiple statistical traffic pattern scenarios.
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